Careers

Requirements:

Strong verification background, including experience developing digital logic verification test benches with strong scripting abilities, writing and evaluating test plans, and experience with UVM (Universal Verification Methodology).

Responsibilities:

Design, develop, and maintain digital logic verification test benches
Create and review test plan documents
Contribute to requirements specifications
Participate in module- and system-level design reviews

• Verilog/SystemVerilog

• UVM

• OOP

• Script Languages (TCL, Python, Perl)

• FPGA IDEs (Vivado, Quartus)

• Communication Interfaces (SPI, I2C, Ethernet, PCIe)

• DO-254