Fundamentals of Digital Design
Verilog Comprehensive
System Verilog for Verification
System Verilog for Design
UVM
HLS Tools
Xilinx Vivado & Vitis Design Environment
Intel Quartus Design Environment
Lattice Diamond Design Environment
Microsemi Libero Design Environment
Efinix Efinity Design Environment
Gowin EDA Design Environment
PCI Express
Ethernet
USB
Transceivers
High Speed Memory
Low Speed Interfaces
Clock Domain Crossing
Pipelining & Resource Sharing
Basic Verification Procedures
Security Critical Designs
Partial Reconfiguration
DSP IPs
Xilinx Based IPs for Video Processing
Linux Basics
Petalinux
Petalinux for Video Processing
Ubuntu FS
Artix 7 & Kintex 7 Architectures
ZYNQ 7000 Architecture
Ultrascale+ Architecture
MPSOC Architecture
RFSOC Architecture
Versal Architecture
Python Development Environment for ZYNQ Architecture
Deep Learning
Xilinx High Level Synthesis
Xilinx XRT
Vitis Vision Library
Vitis AI Library
Vitis OpenCV
Vitis Blas
Vitis Fintech
Intel Cyclone Architecture
Intel SOC Architecture
Arria 10 Architecture
OpenCL Synthesis
C
C++
Python
Perl
Linux Bash Scripting
TCL
Xilinx Amazon AWS
HDL Coder
Model Composer