HDL & verification AC-04
Explore the reusable components and transaction-based communication at the heart of UVM. Connect data modeling, the factory and register models within a consistent verification structure.
Course content
- Data modeling
- UVM classes
- UVM factory
- Transaction-level modeling (TLM)
- Register modeling
Learning focus
Understand reusable verification components; connect transaction modeling and register access to checking.
Applied example
Follow one bus transaction through stimulus, driver, monitor and scoreboard; identify where reusable UVM components connect.
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Examples illustrate course concepts. Tools, hardware and delivery details are agreed for your training.