HDL & verification AC-03
Express hardware intent clearly with SystemVerilog data types, procedural blocks, interfaces and packages. Organize reusable RTL while distinguishing combinational and sequential behavior.
Course content
- Data types
- Procedural always blocks
- User-defined types
- Interfaces
- Packages
Learning focus
Use SystemVerilog types and procedural blocks to express intent; organize reusable interfaces and packages.
Applied example
Describe a controller with explicit state and next-state logic, and examine how type and block choices affect clarity.
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Examples illustrate course concepts. Tools, hardware and delivery details are agreed for your training.